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[AKD4671-B]
AKD4671-B
Evaluation board Rev.0 for AK4671
GENERAL DESCRIPTION AKD4671 is an evaluation board for the AK4671, stereo CODEC with built-in Microphone-Amplifier, Receiver-Amplifier and Headphone-Amplifier. The AKD4671 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D D/A). The AKD4671-B also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4671 --Evaluation board for AK4671 (Cable for connecting with printer port of IBM-AT,compatible PC and control software are packed with this. This control software does not support Windows NT.)
FUNCTION * DIT/DIR with optical input/output * 10pin Header for Digital Audio I/F, PCM I/F (Baseband, Bluetooth) * BNC connector for an external clock input * 10pin Header for serial control mode
REG TVDD3 TVDD2 DVDD PVDD SAVDD AVDD 3.3 V
REG
Opt Out TX Opt In RX
AK4114 DIR DIT
MIC Jack
LIN1/RIN1
Digital Audio I/F 10Pin Header Control I/F 10Pin Header Control I/F SAR ADC 10Pin Header Baseband I/F 10Pin Header VSS2 VSS1 VSS3 VSS4
LIN2/3/4 RIN2/3/4
AK4671
SAIN1/2/3 SAIN3 LOUT1/2/3 ROUT1/2/3 HP Jack 4212 HP GND
Bluetooth I/F 10Pin Header
AK4212
SPK_L Jack SPK_R Jack
Figure 1. AKD4671-B Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual
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[AKD4671-B]
Evaluation Board Manual Operation sequence
1) Set up the power supply lines. (1-1) In case of using the regulator. Set up the jumper pins. JP State JP18 SVDD SEL Short JP20 AVDD SEL Short JP22 SAVDD SEL Short JP24 PVDD SEL Short JP26 DVDD SEL Short JP27 TVDD2 SEL Short JP29 TVDD3 SEL Short JP31 VCC SEL Short JP7 VCC2 SEL Short
Set up the power supply lines. [REG] (red) [D3V] (orange) [AGND] (black) [DGND] (black) = 5.0V = 2.7 3.6V = 0V = 0V : for regulator (3.3V output : AK4671 , Logic) : for AK4114 and logic (typ. 3.3V) : for analog ground : for logic ground
(1-2) In case of using the power supply connectors. Set up the jumper pins. JP State JP18 SVDD SEL Open JP20 AVDD SEL Open JP22 SAVDD SEL Open JP24 PVDD SEL Open JP26 DVDD SEL Open JP27 TVDD2 SEL Open JP29 TVDD3 SEL Open JP31 VCC SEL Open JP7 VCC2 SEL Open
Set up the power supply lines. [SVDD] (orange) [AVDD] (orange) [SAVDD] (orange) [PVDD] (orange) [DVDD] (orange) [TVDD2] (orange) [TVDD3] (orange) [VCC] (orange) [VCC2] (orange) [D3V] (orange) [AGND] (black) [DGND] (black) = 3.0 ~ 5.5V = 2.2 ~ 3.6V = 2.2 ~ 3.6V = 2.2 3.6V = 1.6 3.6V = 1.6 3.6V = 1.6 3.6V = 1.6 3.6V = 1.6 3.6V = 2.7 3.6V = 0V = 0V : for SVDD of AK4212 (typ. 3.6V) : for AVDD of AK4671 (typ. 3.3V) : for SAVDD of AK4671 (typ. 3.3V) : for PVDD of AK4671 (typ. 3.3V) : for DVDD of AK4671 (typ. 3.3V) : for TVDD2 of AK4671 (typ. 3.3V) : for TVDD3 of AK4671 (typ. 3.3V) : for logic (typ. 3.3V : the voltage same as DVDD) : for logic (typ. 3.3V : the voltage same as TVDD2 and TVDD3) : for AK4114 and logic (typ. 3.3V) : for analog ground : for logic ground
* Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4671 and AK4114 should be reset once bringing SW1 (DIR) and SW2 (PDN) "L" upon power-up.
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Evaluation mode 1. Audio I/F evaluation mode
In case of AK4671 evaluation using AK4114, it is necessary to correspond to audio interface format for AK4671 and AK4114. About AK4671's audio interface format, refer to datasheet of AK4671. About AK4114's audio interface format, refer to Table 2 on page 19. The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, please use other mode. In addition, MCLK of AK4114 supports 256fs and 512fs. When evaluate it in a condition except this, please use other modes
(1) External Slave Mode (1-1) Evaluation of A/D using DIT of AK4114 (1-2) Evaluation of D/A using DIR of AK4114 (1-3) Evaluation of Loop-back using AK4114 (1-4) Evaluation of Loop-back that master clock is fed externally, BICK and LRCK are divided with a board (1-5) All interface signals including master clock are fed externally (2) External Master Mode (2-1) Evaluation of A/D using DIT of AK4114 (2-2) Evaluation of D/A using DIR of AK4114 (2-3) Evaluation of Loop-back using AK4114 (2-4) All interface signals including master clock are fed externally (3) PLL Slave Mode (3-1) PLL Reference Clock : MCKI pin (3-1-1) Evaluation of A/D using DIT of AK4114 (3-1-2) Evaluation of Loop-back using AK4114 (3-1-3) All interface signals including master clock are fed externally (3-2) PLL Reference Clock : BICK or LRCK pin (3-2-1) Evaluation of A/D using DIT of AK4114 (3-2-2) Evaluation of D/A using DIR of AK4114 (3-2-3) Evaluation of Loop-back using AK4114 (3-2-4) All interface signals including master clock are fed externally (4) PLL Master Mode (4-1) Evaluation of A/D using DIT of AK4114 (4-2) Evaluation of Loop-back (4-3) All interface signals including master clock are fed externally
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[AKD4671-B]
(1) External Slave Mode When PMPLL bit is "0", the AK4671 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits.
AK4671
MCKO MCKI BICK LRCK SDTO SDTI 256fs, 384fs, 512fs, 768fs or 1024fs 32fs 1fs
DSP or P
MCLK BCLK LRCK SDTI SDTO
(1-1) Evaluation of A/D using DIT of AK4114 X2 (X'tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). The jumper pins should be set as the following.
JP36 MCLK DIR EXT
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
JP35 PHASE THR INV
JP46 4114_MCKI
JP48 M/S Master Slave
(1-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following.
JP36 MCLK DIR EXT
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
JP51 SDTI_SEL DIR ADC
JP35 PHASE THR INV
JP48 M/S
Master
Slave
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[AKD4671-B]
(1-3) Evaluation of Loop-back using AK4114 X2 (X'tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following.
JP36 MCLK DIR EXT
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
JP51 SDTI_SEL DIR ADC
JP35 PHASE THR INV
JP46 4114_MCKI
JP48 M/S Master Slave
(1-4) Evaluation of Loop-back where master clock is fed externally, BICK and LRCK are generated by on-board divider. J12 (EXT) is used . MCLK is supplied from J12 (EXT). BICK and LRCK are generated by 74HC4040 on AKD4671-B. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following.
JP39 EXT DIR EXT DIR 4040 DIR 4040 DIR ADC Master Slave JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL JP51 SDTI_SEL JP48 M/S
When a termination (51) is unnecessary, please set JP39 (EXT) open. JP32 (MKFS), JP34 (BCFS), and JP37 (LRCK) should be set according to the frequency of MCLK, BICK and LRCK. Follows are setting examples in MCLK=256fs , BICK=64fs and LRCK=1fs. When MCLK=384fs or 768fs, JP32, JP34, and JP37 should be set to "384" side. .
JP32 MKFS
256fs 512fs 1024fs 384/768fs MCKO 64fs-384 32fs-384 64fs 32fs
JP34 BCFS
fs-384 fs
JP37 LRCK
(1-5) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following.
JP36 MCLK DIR EXT
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
JP51 SDTI_SEL DIR
JP48 M/S Slave
ADC Maste
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[AKD4671-B]
(2) External Master Mode The AK4671 becomes EXT Master Mode by setting PMPLL bit = "0" and M/S bit = "1". Master clock can be input via MCKI pin, without using on-chip PLL circuit. The clock required to operate is MCKI (256fs, 384fs, 512fs, 768fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits.
AK4671
MCKO MCKI BICK LRCK SDTO SDTI 256fs, 384fs, 512fs, 768fs or 1024fs 32fs or 64fs 1fs
DSP or P
MCLK BCLK LRCK SDTI SDTO
(2-1) Evaluation of A/D using DIT of AK4114 X2 (X'tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19. The jumper pins should be set as the following.
JP36 MCLK DIR EXT
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
JP35 PHASE THR INV
JP46 4114_MCKI
JP48 M/S Master Slave
(2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP). In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19. The jumper pins should be set as the following.
JP36 MCLK DIR EXT
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
JP51 SDTI_SEL DIR ADC
JP35 PHASE THR
JP48 M/S Slave
INV Master
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[AKD4671-B]
(2-3) Evaluation of Loop-back using AK4114 X'tal (X2) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following.
JP36 MCLK DIR EXT
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
JP51 SDTI_SEL DIR ADC
JP35 PHASE THR INV
(2-4) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following.
JP36 MCLK DIR EXT
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
JP51 SDTI_SEL DIR
JP48 M/S Slave
ADC Master
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[AKD4671-B]
(3) PLL Slave Mode A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4671 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits.
(3-1) PLL Reference Clock : MCKI pin
11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
AK4671
MCKI MCKO BICK LRCK SDTO SDTI
DSP or P
256fs/128fs/64fs/32fs 32fs 1fs
MCLK BCLK LRCK SDTI SDTO
(3-1-1) Evaluation of A/D using DIT of AK4114 J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). X'tal oscillator should be removed from X2. The jumper pins should be set as the following.
JP39 EXT DIR EXT
JP36 MCLK
JP33 BICK_SEL
JP38 LRCK_SEL
JP46 4114_MCKI
JP35 PHASE
JP7 MCKO
DIR
4040
DIR
4040
THR
INV
JP48 M/S Master Slave
When a termination (51) is unnecessary, please set JP39 (EXT) to open.
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[AKD4671-B]
(3-1-2) Evaluation of Loop-back using AK4114 J12 (EXT) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). X'tal oscillator should be removed from X2. The jumper pins should be set as the following.
JP39 EXT DIR EXT DIR 4040 DIR 4040 THR INV DIR ADC JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL
JP7 MCKO
JP48 M/S Master Slave
When a termination (51) is unnecessary, please set JP39 (EXT) open.
(3-1-3) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following.
JP36 MCLK DIR EXT DIR 4040 DIR 4040 THR INV DIR ADC JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL
JP39 EXT
JP48 M/S Master Slave
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[AKD4671-B]
(3-2) PLL Reference Clock : BICK or LRCK pin
AK4671
MCKO MCKI BICK LRCK SDTO SDTI 32fs or 64fs 1fs BCLK LRCK SDTI SDTO
DSP or P
(PLL Reference Clock: BICK pin)
AK4671
MCKO MCKI BICK LRCK SDTO SDTI 32fs 1fs BCLK LRCK SDTI SDTO
DSP or P
(PLL Reference Clock: LRCK pin)
(3-2-1) Evaluation of A/D using DIT of AK4114 X2 (X'tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). The jumper pins should be set as the following.
JP46 4114_MCKI JP35 PHASE JP48 M/S
JP39 EXT DIR EXT
JP36 MCLK
JP33 BICK_SEL
JP38 LRCK_SEL
DIR
4040
DIR
4040
THR
INV
Master
Slave
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[AKD4671-B]
(3-2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following.
JP39 EXT DIR EXT JP48 M/S Master Slave DIR 4040 DIR 4040 THR INV DIR ADC JP36 MCLK JP33 BICK_SEL JP38 LRCK_SEL JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL
(3-2-3) Evaluation of Loop-back using AK4114 X2 (X'tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following.
JP39 EXT DIR EXT JP48 M/S Master Slave
JP36 MCLK
JP33 BICK_SEL
JP38 LRCK_SEL
JP46 4114_MCKI
JP35 PHASE
JP51 SDTI_SEL
DIR
4040
DIR
4040
THR
INV
DIR
ADC
(3-2-4) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following.
JP35 PHASE JP51 SDTI_SEL
JP39 EXT DIR EXT
JP36 MCLK
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
JP46 4114_MCKI
THR
INV
DIR
ADC
JP48 M/S Master Slave
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[AKD4671-B]
(4) PLL Master Mode When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit.
AK4671
MCKI MCKO BICK LRCK SDTO SDTI
11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
DSP or P
256fs/128fs/64fs/32fs 32fs, 64fs 1fs
MCLK BCLK LRCK SDTI SDTO
(4-1) Evaluation of A/D using DIT of AK4114 J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP). X'tal oscillator should be removed from X2. In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19. The jumper pins should be set as the following.
JP39 EXT DIR EXT JP48 M/S Master Slave
JP36 MCLK
JP33 BICK_SEL
JP38 LRCK_SEL
JP46 4114_MCKI
JP35 PHASE
JP7 MCKO
DIR
4040
DIR
4040
THR
INV
When a termination (51) is unnecessary, please set JP39 (EXT) open.
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[AKD4671-B]
(4-2) Evaluation of Loop-back J12 (EXT) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). X'tal oscillator should be removed from X2. The jumper pins should be set as the following.
JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL
JP39 EXT DIR EXT JP48 M/S Master Slave
JP36 MCLK
JP33 BICK_SEL DIR 4040
JP38 LRCK_SEL DIR 4040
THR
INV
DIR
ADC
When a termination (51) is unnecessary, please set JP39 (EXT) open.
(4-3) All interface signals including master clock are fed externally PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT). The jumper pins should be set as the following.
JP46 4114_MCKI JP35 PHASE JP51 SDTI_SEL
JP39 EXT DIR EXT JP48 M/S Master Slave
JP36 MCLK
JP33 BICK_SEL
JP38 LRCK_SEL
DIR
4040
DIR
4040
THR
INV
DIR
ADC
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[AKD4671-B]
2. PCM I/F evaluation mode
A reference clock of PLLBT is selected among the input clocks to SYNCA, BICKA, SYNCB or BICKB pin. The required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by PMPCM bit. Input frequency is selected by PLLBT2-0 bits. BCKO2 bit select the output clock frequency of BICKA or BICKB pin. AK4671 does not support master mode for both PCM I/F A and B nor slave mode for both PCM I/F A and B. When PMPCM bit is "0", SYNCA, BICKA, SYNCB and BICKB pins are Hi-Z.
(1) PLLBT reference clock: SYNCA or BICKA pin (1-1) SYNCA and BICKA are fed from on-board clock generator. (1-2) SYNCA and BICKA are fed externally via PORT3 (Baseband Module). (2) PLLBT reference clock: SYNCB or BICKB pin (2-1) SYNCB and BICKB are fed from on-board clock generator. (2-2) SYNCB and BICKB are fed externally via PORT6 (Bluetooth Module).
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[AKD4671-B]
(1) PLLBT reference clock: SYNCA or BICKA pin The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output via SYNCB and BICKB pins.
AK4671
SYNCA BICKA SDTOA SDTIA 1fs2 16fs2
Baseband Module
SYNC BICK SDTI SDTO
Bluetooth Module
SYNCB BICKB SDTOB SDTIB 1fs2 16fs2 or 32fs2 SYNC BICK SDTI SDTO
(PLLBT Reference Clock: SYNCA or BICKA pin)
(1-1) SYNCA and BICKA are fed from on-board clock generator. X1 (X'tal), PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used. The jumper pins should be set as the following. Please set JP42 (BCFS2) to the required frequency. Follows are setting in BICKA=32fs. When clocks are supplied from J13 (EXT1) without using X1, JP41 (MCLK2) should be set to "EXT1".
JP40 XTE XTL EXT1
JP41 MCLK2
256fs2 128fs2 64fs2 32fs2 16fs2
JP42 BCFS2
JP43 BICK2_SEL
JP45 LRCK2_SEL
JP49 PLLBT
BICKA BICKB
LRCKA LRCKB
BICKA BICKB
JP62 BICKA
JP63 SYNCA
JP64 BICKB
JP65 SYNCB
JP61 SDTIB
JP60 SDTIA
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[AKD4671-B]
JP47 (BICKA PHASE) is jumper which decides polarity of BICKA, "THR" or "INV" should be selected according to the PCM I/F format. JP54 (BICKB PHASE) should be set to "THR".
JP47 BICKA PHASE JP54 BICKB PHASE
THR
INV
THR
INV
In case of loop-back "SDTOA SDTIA" and "SDTOB SDTIB", please set JP50 (SDTOA LOOP) and JP55 (SDTOB LOOP) short.
JP50 SDTOA LOOP
JP55 SDTOB LOOP
(1-2) SYNCA and BICKA are fed externally via PORT3 (Baseband Module). PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used. SYNCA and BICKA should be supplied from PORT3. The jumper pins should be set as the following.
JP40 XTE XTL EXT1
JP41 MCLK2
JP43 BICK2_SEL
JP45 LRCK2_SEL
JP49 PLLBT
BICKA BICKB
LRCKA LRCKB
BICKA BICKB
JP47 (BICKA PHASE) is jumper which decides polarity of BICKA, "THR" or "INV" should be selected according to the PCM I/F format. JP54 (BICKB PHASE) should be set to "THR".
JP47 BICKA PHASE JP54 BICKB PHASE
THR
INV
THR
INV
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[AKD4671-B]
(2) PLLBT reference clock: SYNCB or BICKB pin The PLLBT circuit generates the required clock for PCM I/F from SYNCB or BICKB. Generated clocks are output via SYNCA and BICKA pins.
AK4671
SYNCA BICKA SDTOA SDTIA 1fs2 16fs2 or 32fs2
Baseband Module
SYNC BICK SDTI SDTO
Bluetooth Module
SYNCB BICKB SDTOB SDTIB 1fs2 16fs2 SYNC BICK SDTI SDTO
(PLLBT Reference Clock: SYNCB or BICKB pin)
(2-1) SYNCB and BICKB are fed from on-board clock generator. X1 (X'tal), PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used. The jumper pins should be set as the following. Please set JP42 (BCFS2) to the required frequency. Follows are setting in BICKB=32fs. When clocks are supplied from J13 (EXT1) without using X1, JP41 (MCLK2) should be set to "EXT1".
JP49 PLLBT
JP40 XTE XTL EXT1
JP41 MCLK2
256fs2 128fs2 64fs2 32fs2 16fs2
JP42 BCFS2
JP43 BICK2_SEL
JP45 LRCK2_SEL
BICKA BICKB
LRCKA LRCKB
BICKA BICKB
JP62 BICKA
JP63 SYNCA
JP64 BICKB
JP65 SYNCB
JP61 SDTIB
JP60 SDTIA
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[AKD4671-B]
JP54 (BICKB PHASE) is jumper which decides polarity of BICKB, "THR" or "INV" should be selected according to the PCM I/F format. JP47 (BICKA PHASE) should be set to "THR".
JP47 BICKA PHASE
JP54 BICKB PHASE
THR
INV
THR
INV
In case of loop-back "SDTOA SDTIA" and "SDTOB SDTIB", please set JP50 (SDTOA LOOP) and JP55 (SDTOB LOOP) short.
JP50 SDTOA LOOP JP55 SDTOB LOOP
(2-2) SYNCB and BICKB are fed externally via PORT6 (Bluetooth Module). PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used. Please supply SYNCB and BICKB from PORT6. The jumper pins should be set as the following.
JP40 XTE XTL EXT1
JP41 MCLK2
JP43 BICK2_SEL
JP45 LRCK2_SEL
JP49 PLLBT
BICKA BICKB
LRCKA LRCKB
BICKA BICKB
JP54 (BICKB PHASE) is jumper which decides polarity of BICKB, "THR" or "INV" should be selected according to the PCM I/F format. JP47 (BICKA PHASE) should be set to "THR".
JP47 BICKA PHASE
JP54 BICKB PHASE
THR
INV
THR
INV
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[AKD4671-B]
DIP Switch set up
[S1] (SW DIP-6): Mode setting for AK4671 and AK4114. No. 1 2 3 4 5 6 Name DIF2 DIF1 DIF0 OCKS1 CAD0 I2C ON ("H") OFF ("L") Default ON OFF OFF OFF OFF ON
AK4114 Audio Format Setting See Table 2 AK4114 Master Clock Setting : See Table 3 AK4671 Control Mode Setting See Table 4 Table 1. Mode Setting for AK4671 and AK4114
DIF2 0 0 0 0 1 1 1 1
DIF1 0 0 1 1 0 0 1 1
DIF0 0 1 0 1 0 1 0 1
DAUX 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S
SDTO 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S
LRCK H/L O H/L O H/L O H/L O H/L O L/H O H/L I L/H I
BICK 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs
O O O O O O I I
Default
Table 2. Setting for AK4114 Audio Interface Format
OCKS1 0 1
MCKO1 256fs 512fs
X'tal 256fs 512fs
Default
Table 3. Setting for AK4114 Master Clock
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[AKD4671-B]
Other jumper pins set up
Sub Board [JP1] (RIN2) : RIN2 input. GND : In case of full-differential input. MPWR : MIC-power is supplied to RIN2. OPEN : MIC-power is not supplied to RIN2. [JP2] (LIN1) : LIN1 input. SHORT : MIC-power is supplied to LIN1. OPEN : MIC-power is not supplied to LIN1. [JP3] (LIN2) : LIN2 input. SHORT : MIC-power is supplied to LIN2. OPEN : MIC-power is not supplied to LIN2. [JP4] (RIN1) : RIN1 input. GND : In case of full-differential input. MPWR : MIC-power is supplied to RIN1. OPEN : MIC-power is not supplied to RIN1. [JP5] (PVDD) : PVDD of AK4212 power supply. SHORT : PVDD is supplied from "PVDD" jack. OPEN : PVDD is not supplied from "PVDD" jack [JP6] (PDN) : PDN of AK4212. SHORT : PDN is supplied from SW2 (PDN). OPEN : PDN is not supplied from SW2 (PDN). [JP7] (MCKO) : MCKO output. SHORT : When AK4671 outputs MCKO. OPEN : When AK4671 does not output MCKO. [JP8] (SDA) : SDA of AK4212. SHORT : SDA is supplied from PORT5 (CTRL). OPEN : SDA is not supplied from PORT5 (CTRL). [JP9] (SCL) : SCL of AK4212. SHORT : SCL is supplied from PORT5 (CTRL). OPEN : SCL is not supplied from PORT5 (CTRL). [JP10] (TVDD) : TVDD of AK4212 power supply. SHORT : TVDD is supplied from "DVDD" jack. OPEN : TVDD is not supplied from "DVDD" jack [JP11] (AVDD) : AVDD of AK4212 power supply. SHORT : AVDD is supplied from "AVDD" jack. OPEN : AVDD is not supplied from "AVDD" jack [JP12] (U2 RIN1) : RIN1 of AK4212 input SHORT : RIN1 is supplied from ROUT2. OPEN : RIN1 is not supplied from ROUT2. [JP13] (U2 LIN1) : LIN1 of AK4212. SHORT : LIN1 is supplied from LOUT2. OPEN : LIN1 is not supplied from LOUT2.
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[AKD4671-B]
[JP14] (U2 SPRIN) : SPRIN of AK4212. SHORT : SPRIN is supplied from ROUT3. OPEN : SPRIN is not supplied from ROUT3. [JP15] (U2 SPLIN) : SPLIN of AK4212. SHORT : SPLIN is supplied from LOUT3. OPEN : SPLIN is not supplied from LOUT3.
Main Board [JP30] (GND) : AGND and DGND. SHORT : Common. OPEN : Separated. [JP46] (4114_MCKI) : MCKI of AK4114. SHORT : MCKO of AK4671. OPEN : X'tal (X2). [JP56] (D3V) : Power supply of PORT7 SHORT : It is supplied from "D3V" jack. OPEN : It is not supplied from "D3V" jack. [JP57] (I2C PIN) : AK4671 I2C input. I2C : It is supplied from S1 (I2C). MCLK2 : It is supplied from MCLK2.
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[AKD4671-B]
The function of the toggle SW
[SW2] (PDN) : Power down of AK4671. Keep "H" during normal operation. [SW1] (DIR) : Power down of AK4114. Keep "H" during normal operation. Keep "L" when AK4114 is not used.
Indication for LED
[LED1] (ERF) : Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4671 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT5 (CTRL) with PC by 10 wire flat cable packed with the AKD4671.Table 4 shows switch and jumper settings for serial control. I2C Mode should be selected in Table 4. Note) When evaluate it in SAR-ADC of AK4671, 4-WIRE Mode should be selected in Table 4.
PC
PORT5 CSN Connect CCLK/SCL CDTI/SDA AKD4671 CDTO/SDA 10 wire flat cable 10pin Connector 10pin Header
Figure 2. Connect of 10 wire flat cable
Mode 4-WIRE CAD0=0 I2C CAD0=1
S1 (DIP SW) JP52 I2C CAD0 CTRL_SEL 4-WIRE OFF OFF ON OFF I2C ON ON Table 4. Serial Control Setting
JP53 CTRL_SEL2 4-WIRE I2C Default
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[AKD4671-B]
Analog Input/Output Circuits
(1) Input Circuits (1-1) LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuit
J2 1 2 3 LIN1/RIN1 JP23 2 3 4 5 LIN2 LIN1 RIN1
J5 LIN
C50 1u 1 +
R39
(short)
LIN2 LIN3 LIN4
LIN_SEL
LIN3
LIN4 RIN2
JP25 2 3 4 5
J7 RIN
C53 1u 1 +
R42
(short)
RIN2 RIN3 RIN4
RIN_SEL
RIN3
RIN4
Figure 3. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuit LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 share J5/J7. JP23 (LIN_SEL) and JP25 (RIN_SEL) select each path.
(1-2) SAIN1, SAIN2 and SAIN3 Input Circuit
JP28 2 3 4 5 SAIN1
J9 SAIN
1
SAIN1 SAIN2 SAIN3
SAIN_SEL
SAIN2
SAIN3
2 3 4 5
J11 SAIN3
1
Figure 4. SAIN1, SAIN2 and SAIN3 Input Circuit SAIN1, SAIN2 and SAIN3 share J9. JP28 (SAIN_SEL) select each path.
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[AKD4671-B]
(2) Output Circuits (2-1) LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 Output Circuit
JP16 LOUT3 LOUT2 LOUT1
LOUT3
+
R32
LOUT2 LOUT1
LOUT_SEL
220
R33
1
J1 LOUT
C44 1u
20k
2 3 4 5
JP17 HPL JACK
R34
+
(short)
C45 100u
R35 16
J3 1 JP58 L_16ohm 2 3 HP
JP19 HPR JACK
R37
+
(short)
C47 100u
R36 16
JP59 R_16ohm R38
JP21 ROUT3 ROUT2 ROUT1
ROUT3
+
ROUT2 ROUT1
ROUT_SEL
220
R40
1
J4 ROUT
2 3 4 5
C49 1u
20k
Figure 5. LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 Output Circuit LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 share J1/J4. JP16 (LOUT_SEL) and JP21 (ROUT_SEL) select each path.
(2-2) Headphone of AK4212 Output Circuit JP13 (U2LIN1) and JP12 (U2RIN1) on sub board should be shorted, and LOUT2S and ROUT2S signal should be input to Headphone-Amp block of AK4212.
JP13 U2LIN1 JP12 U2RIN1
R43
HPL (short)
R44 J10 1 2 3
HPR (short)
4212 HP
Figure 6. Headphone of AK4212 Output Circuit
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[AKD4671-B]
(2-3) Speaker of AK4212 Output Circuit JP15 (U2SPLIN) and JP14 (U2SPRIN) on sub board should be shorted, and LOUT3 and ROUT3 signal should be input to Speaker-Amp block of AK4212.
JP15 U2SPLIN
JP14 U2SPRIN
LOUTP
J6 1 2 3 SPK_L J8
LOUTN
ROUTP
1 2 3 SPK_R
ROUTN
Figure 7. Speaker of AK4212 Output Circuit
* AKM assumes no responsibility for the trouble when using the above circuit examples.
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[AKD4671-B]
Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4671-B according to previous term. 2. Connect IBM-AT compatible PC with AKD4671-B by 10-line type flat cable (packed with AKD4671-B). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4671-B Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4671.exe" and "AKD4212 .exe" to set up the control program. In case of evaluation using AK4212, "AKD4212 .exe" is necessary. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button
Explanation of each buttons
[Port Reset] : [Write default] : [All Write] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5]: [SAVE] : [OPEN] : [Write] : [Filter] : [5 Band EQ] : Set up the USB interface board (AKDUSBIF-A) . Initialize the register of AK4671. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Set Programmable Filter (FIL1, FIL3, EQ) of AK4671 easily. Set 5Band Equalizer of AK4671 easily.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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[AKD4671-B]
Explanation of each dialog 1. [Write Dialog] : Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4671, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4671, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4671 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4671, click [OK] button. If not, click [Cancel] button.
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[AKD4671-B]
4. [Save] and [Open]
4-1. [Save] Save the current register setting data. The extension of file name is "akr". (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is "akr". 4-2. [Open] The register setting data saved by [Save] is written to AK4671. The file type is the same as [Save]. (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button.
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[AKD4671-B]
5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is "aks".
Figure 8. Window of [F3]
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[AKD4671-B]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 9. opens.
Figure 9. [F4] window
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2007 / 05
[AKD4671-B]
6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 10.
Figure 10. [F4] window (2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The sequence file names can assign be saved. The file name is *.ak4. [OPEN] : The sequence file names assign that are saved in *.ak4 are loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
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[AKD4671-B]
7. [Function5 Dialog]
The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 11.opens.
Figure 11. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 12. (2) Click [WRITE] button, then the register setting is executed.
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2007 / 05
[AKD4671-B]
Figure 12. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded. 7-3. Note (1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change.
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2007 / 05
[AKD4671-B]
8. [Filter Dialog]
This dialog can easily set the AK4671's programmable filter. A calculation of a coefficient of Digital Programmable Filter such as HPF,EQ filter ,a write to a register and check frequency response. Window to show to Figure 13 opens when push a [Filter] button .
Figure 13. [Filter] window
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2007 / 05
[AKD4671-B]
8-1. Setting of a parameter (1) Please set a parameter of each Filter. Item Sampling Rate FIL3 Cut Off Frequency Filter type Gain HPF Cut Off Frequency LPF Cut Off Frequency EQ for Gain Compensation (EQ0) Pole Frequency Zero-point Frequency Gain 5 Band Equalizer EQ1-5 Center Frequency Contents Sampling frequency (fs) Stereo separation emphasis filter cut off frequency Type of stereo separation emphasis filter Gain of stereo separation emphasis filter High pass filter cut off frequency Setting range 7350Hz fs 48000Hz fs/10000 Cut Off Frequency (0.497 * fs) LPF or HPF -10dB Gain 0dB fs/10000 Cut Off Frequency (0.497 * fs) fs/20 Cut Off Frequency (0.497 * fs) fs/10000 Pole Frequency (0.497 * fs) fs/10000 Zero-point Frequency (0.497 * fs) 0dB Gain +12dB 0Hz Center Frequency < (0.497 * fs) 1Hz Band Width < (0.497 * fs) -1 Gain < 3
Low pass filter cut off frequency
Pole Frequency Zero-point Frequency Gain EQ1-5 Center Frequency
EQ1-5 Band Width EQ1-5 Band Width ( Note 1) EQ1-5 Gain EQ1-5 Gain ( Note 2) Note 1. Bandwidth where the gain gap is 3dB compared with center frequency. Note 2. When a gain is smaller than "0", EQ becomes a notch filter.
(2) Please set ON/OFF of Filter with check buttons of "FIL3", "EQ0", "LPF", "HPF", "HPFAD", "EQ1", "EQ2", "EQ3", "EQ4", "EQ5". When the button is checked, Filter becomes ON. When "Notch Filter Auto Correction" is checked, automatic compensation is executed for center frequency of notch filter. ("Cf. 8-4. automatic compensation for center frequency of a notch filter")
Figure14. Filter ON/OFF setting button
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[AKD4671-B]
8-2. A calculation of a register A register setting values are displayed when [Register Setting] button is clicked. When any value is set to out of range, error message is displayed, and a calculation of register setting is not executed.
Figure15. A register setting calculation result In the following cases, a register set values are updated.
(1) When [Register Setting] button was pushed. (2) When [Frequency Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button "Notch Filter Auto Correction"
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2007 / 05
[AKD4671-B]
8-3.Indication of a frequency characteristic A frequency characteristic is displayed when [Frequency Response] button is clicked. The register values are updated at the same time. If "Frequency Range" is changed, and [UpDate] button is clicked, indication of a frequency characteristic is updated.
Figure16. A frequency characteristic indication result In the following cases, a register set values are updated.
(1) When [Register Setting] button was pushed. (2) When [Frequency Response] button was pushed. (3) When [UpDate] button was pushed on a frequency characteristic indication window. (4) When set ON/OFF of a check button "Notch Filter Auto Correction"
8-4. Automatic compensation for center frequency of a notch filter When a gain of 5 band Equalizer is set to "-1", Equalizer becomes a notch filter. When center frequency of several notch filters are near frequency each other, center frequency error occurs (Figure 17). When "Notch Filter Auto Correction" button is checked, automatic compensation is executed for center frequency of a notch filter. Register setting and frequency characteristics are displayed after automatic compensation (Figure18). This automatic compensation is available for EqualizerBand where a gain is set to "-1". (Note) When distance among center frequencies is smaller than band width, there is a possibility that automatic compensation does not operate normally. Please confirm a compensation result by indication of a frequency characteristic.
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2007 / 05
[AKD4671-B]
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common) Figure17. When there is no compensation of center frequency
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common) Figure18. When there is compensation of center frequency
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2007 / 05
[AKD4671-B]
9. [5 Band EQ Dialog]
This dialog can easily set the AK4671's 5-Band Equalizer.
Figure 19. [5 Band EQ] window When the check box of "5 Band EQ" is checked, 5-Band Equalizer is ON (EQ bit = "1"). When the slide button is changed, its value is written to the internal register immediately.
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2007 / 05
[AKD4671-B]
Revision History
Date (YY/MM/DD) 07/05/15 Manual Revision KM089000 Board Revision 0 Reason First Edition Contents
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
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2007 / 05
A
B
C
D
E
SAIN1 SAIN2 SAIN3
LIN1
RIN1
LIN2
RIN2
LIN3
RIN3
LIN4
RIN4
4670_AVDD
4670_TVDD2 4670_PVDD
80pin_4 CN4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
1
1
1
1
1
1
1
1
1
1
GND
E
JP1 RIN2 R1
1
TP9 TP10 TP11 SAIN1 SAIN2 SAIN3
TP1 LIN1
TP2 RIN1
TP3 LIN2
TP4 RIN2
TP5 LIN3
TP6 RIN3
TP7 LIN4
TP8 RIN4 AVDD
E
MPWR
61
CN3
1
GND
JP4 RIN1
R2 2.2k R3 2.2k R4 2.2k 2.2k
JP3LIN2
SPLIN
TP18 LOUT3 TP19 ROUT3 TP16 LOUT2 TP15 ROUT2 TP12 LOUT1 TP13 ROUT1
58 60
LOUT3
MPWR
JP2LIN1
1
59
ROUT3
TP45 VSS1
TP46 AVDD
1
1
1
SPRIN
LOUT2
1
1
TP40 MPWR
1
57
ROUT2
56
LOUT1
R5 open
1
55
ROUT1
C2 1u
D
C3 1u +
U1
C39 10u
54
D
C3
B8
A2
A3
A4
B2
B3
B4
B5
A5
B6
A6
A7
B7
A8
VSS1
NC
ROUT1/RCN
ROUT3/LON
RIN1/IN1-
RIN2/IN2-
RIN3/IN3-
RIN4/IN4-
LOUT1/RCP
LOUT3/LOP
LIN1/IN1+
LIN2/IN2+
LIN3/IN3+
LIN4/IN4+
AVDD
CN1
MDT TP41
1
C36 0.1u
TP21 HPR
53
TP34 TEST
TEST 1 A9
1
52
HPR
A1 1 B1 2
MDT
TP23 HPL
51
MPWR
LOUT2
B9
1
C7
C9
50
HPL
1
TP24 SAVDD
C1
4670_SAVDD
SAIN3
ROUT2
TP22 MUTET + C8
JP5 PVDD C10 PDN JP6
49
1
+
3 C2 4 D1 5 D2 SAVDD VCOC D8 SAIN1 VCOM D9 0.1u SAIN2 MUTET C8
10u C9
C6 1u C35 2.2u C38 +
1
48
16
14
11
13
15
12
10
U2
9
TP44 VCOM TP43 VCOC
1
2.2u 0.1u
PVSS
2.2u
PDN
CP 47
HPR
HPL
RIN4/IN4+
PVDD
PVEE
CN
R16
PDN 8 46
C
1
6
TP26 VSS3
C12 + 10u C17 10u +
17
C13 0.1u C16 0.1u
TP20 VCOCBT
VSS3
LIN4/IN4-
1
1
E2 8
TVDD3
PVDD
E8
51 R20
19 LIN3/IN3CCLK/SCL 6
JP9 SCL SCL JP10
1
4670_TVDD3
7
TP27 TVDD3
AK4671
VCOCBT
1
E1
E9
51 R18
18
C
JP8 SDA SDA
TP14 PVDD TP17 VSS2
R6 10k C1 4.7n
R27 10k C40 4.7n
RIN3/IN3+
CDTI/SDA
7
R19 220k
TP25 LOUTN
45
44
LOUTN
F2
4670_SDTOB
SDTOB
VSS2
F9
1
F1
4670_SYNCB
SYNCB
TVDD2
F8
TP28 TVDD2
21 RIN2/IN2+
10
AK4212
C18 0.1u
AVSS 4
+ + +
C19 10u C23 10u
TVDD
1T
1
9
TP61 P61 BICKB
51 R11
G2 BICKB SDTOA G9 22 H9
1T
4670_BICKB
11
TP60 51 P60 SDTIB R14 51
1T
G1
4670_SDTIB
SDTIB
SYNCA
JP12 U2 RIN1
1T
12
H1 13
SDTI
BICKA
G8
ROUTN
ROUTP
LOUTN
LOUTP
CSN/CAD0
CCLK/SCL
4670_SDTI
B
14
MCKO
DVDD
CDTO
GPO2
SDTO
LRCK
VSS4
MCKI
BICK
PDN
I2C
4670_SDTO
TP35 51 P35 SDTO R25 TP48 51 P48 LRCK R23 TP49 P49 BICK TP42 MCKI TP36 MCKO 51 R21 51 R17 51 R15 51 C11 (open)
CDTI/SDA
GPO1
SDTIA
1T
MIXL
R26
1
J1
J8
SPLIN
SVDD
SVSS
TP39 SDTI
TP31 GPO1
1
25
26
27
28
29
30
31
32
15
C31 TP33 GPO2 0.1u +
1
J2
J3
J4
J5
J6
J7
H2
H3
H4
H5
H6
H7
4670_LRCK
16
1T
C24 0.1u C25 + TP37 DVDD
1
1T
H8
J9
4670_BICK
17
R28 51
R29 51
C33 10u R30 51 SPLIN R24
1
4670_MCKI 4670_MCKO
18
JP15 U2 SPLIN
1
1
1
JP7 MCKO
19
R31 51
10u
TP30 VSS4
R7 51
R9 51
R10 R8 51 51
20
PDN SCL 80pin_1 SDA DVDD
1T 1T 1T 1T 1T 1 1 1 1 1 1 1 1
A
TP51 P51 PDN
TP50 I2C
TP55 TP52 CDTO CSN
TP53 TP54 P53 CCLK CDTI
TP62 TP64 TP63 TP65 P62 SDTIA BICKA SYNCA SDTOA
TP56 P56 ROUTN
TP57 ROUTP
CN2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4670_PDN 4670_I2C
A
CSN/CAD0 4670_CDTO
CDTI/SDA
4670_DVDD
4670_SDTIA
4670_SYNCA 4670_SDTOA
ROUTN
CCLK/SCL
B
4670_BICKA
ROUTP
+
TP58 51 P58 SYNCB R12
C20 0.1u
C21 10u
2.2u
JP13 U2 LIN1
TP47 P47 SVDD
SVDD
C
+
TP59 SDTOB R13
C5 0.1u
1
+
C4 10u
C14
C15 0.1u
20 VREF TVDD 5
51
1
DVDD
TP29 LOUTP
43
42
LOUTP
C22 0.1u
LIN2/IN2AVDD 3
JP11 AVDD AVDD
41
TP32 P32 SPRIN
C26 0.22u C27 0.22u + +
24
+ +
23 RIN1/IN1+ SPRIN 2 LIN1/IN1MIXR 1
80pin_3
TP38 SPLIN
B
C34 0.015u
1k C37 0.033u
JP14 SPRIN U2 SPRIN
R22 1k
C28 0.015u
C29 0.033u
A
Title Size Document Number
AKD4671-B
AK4671
Sheet Rev
A2
Date:
D
0 1
of
Wednesday, April 04, 2007
E
5
A
B
C
D
E
E
T1 TA48033F IN C41 0.1u GND REG1
1
E
T45_RED
C42 + 0.1u
1
OUT
C43 47u LOUT3 LOUT2 J2 LOUT1
1 2 3
T45_BK LIN1 RIN1
LOUT2 LOUT1 LOUT_SEL
+
AGND1
LOUT3
JP16
2
1
R32 220
1
J1 LOUT
2 3 4 5
C44 1u +
R33 20k
SVDD1
L1 (short)
1 1 2 1
JP18 SVDD_SEL SVDD
LIN1/RIN1
JP17 R34 HPL JACK (short)
C45 100u
R35 16
1
T45_OR
J3
+
2
C46 47u JP20 AVDD_SEL
2
JP58 L_16ohm + LIN2 LIN2 LIN3 LIN4 LIN_SEL LIN4 4670_SAVDD
2 3
AVDD1
L2
1 1 1
4670_AVDD
2 3 4 5
T45_OR
D
+
2
C48 47u
(short)
J5 LIN
1
C50 1u +
R39 (short)
JP23
JP19 HPR JACK
R37 (short)
C47 100u
R36 16 JP59 R_16ohm
HP
LIN3 ROUT3 ROUT2 ROUT1 ROUT3 ROUT2 ROUT1 ROUT_SEL JP21 +
SAVDD1
L3
1 1 1 2
JP22 SAVDD_SEL
R38 220
1
J4 ROUT
2 3 4 5
D
T45_OR
+
2
C51 47u
(short)
C49 1u
R40 20k
PVDD1
L4
1 1 1 2
JP24 PVDD_SEL 4670_PVDD J7 RIN R41 10 JP26 DVDD_SEL
2 2 3 4 5 1
T45_OR
+
2
C52 47u
(short)
C53 1u +
R42 (short)
JP25 RIN2 RIN3 RIN4 RIN_SEL
RIN2 LOUTP J6 RIN4
1
RIN3
DVDD1
L5
1 1 1
LOUTN 4670_DVDD
2 3
T45_OR
+
2
C54 47u
(short) ROUTP
1 2 3
SPK_L J8
C
C
TVDD2
L6
1 1 1 2
JP27 TVDD2_SEL 4670_TVDD2
2 3 4 5
J9 SAIN
1
JP28 SAIN1 SAIN2 SAIN3 SAIN_SEL
SAIN1
SPK_R SAIN2 ROUTN SAIN3
T45_OR
+
2
C55 47u
(short)
TVDD3
L7
1 1 1 2
JP29 TVDD3_SEL 4670_TVDD3 J11 SAIN3
2 3 4 5 1
T45_OR
+
2
C56 47u
(short)
R43 HPL (short)
1
JP30 GND VCC1
1 1 1
L8
2
JP31 VCC_SEL VCC HPR
J10
R44
2 3
T45_OR
+
2
C57 47u
(short)
(short) 4212 HP
B
VCC2
L11
1 1 1 2
JP66 VCC2_SEL VCC2
B
T45_OR
+
2
C96 47u
(short)
D3V1
L9
1 1 1 2
D3V
T45_OR
+
2
C58 47u
(short)
DGND1
1
T45_BK
A
A
Title Size Document Number
AKD4671-B
Power Supply, I/O
Sheet Rev
A2
Date:
A B C D
0
of
Wednesday, April 04, 2007
E
2
5
A
B
C
D
E
E
E
D3V
EXT_MCLK
4114_BICK JP32 4114_MCKO JP36 MCLK
1 2 3 4 5 6 14 13 12 11 10 9 8
EXT_BICK JP33 DIR BICK_SEL 4040
EXT_LRCK THR JP35 INV PHASE
J12 EXT
2 3 4 5 1
DIR R45 51 JP39 EXT EXT
1CLR 2CLR 1D 2D 1CK 2CK 1PR 2PR 1Q 2Q 1Q 2Q Vcc GND
256fs 512fs 1024fs 384/768fs MCKO MKFS
JP34
10 11 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 VD Q9 Q10 Q11 DGND Q12 RST CLK 9 7 6 5 3 2 4 13 12 14 15 1
64fs-384 32fs-384 64fs 32fs fs-384 fs JP37 LRCK BCFS
4040 JP38 DIR LRCK_SEL
A K
LED1 ERF R46 1k
16
C59 0.1u
7
C60 0.1u
8
D
U3 74AC74
3 4 5 6 10 7 2 9 1 A B C D QA QB QC QD Carry 14 13 12 11 15
U4 74HC4040 4114_LRCK
1 2 3 4 5 6 14 1A 1Y 2A 2Y 3A 3Y Vcc GND 3 4Y 4A 5Y 5A 6Y 6A 8 9 10 11 12 13
D
4114_INT0 4114_PDN
ENT ENP Vcc CLK LOAD CLR GND
16
7
8
U5
74AC163
C63 0.1u
L
1 2
C62 0.1u
C61 0.1u
U6 74HC14
A
MCKO
R47 10k
K
D1 HSU119
H SW1 DIR
8 9 10 11 12 13
VCC U7 74HCU04
GND Vcc 1 2 3 4 5 6 14 7 8 9 10 11 12 13
4Y 4A 5Y 5A 6Y 6A
C
14
1A 1Y 2A 2Y 3A 3Y Vcc GND
4Y 4A 5Y 5A 6Y 6A
1A 1Y 2A 2Y 3A 3Y
4670_PDN
C
1 2 3 4 5 6
7
C64 0.1u C65 0.1u
R48 10k
K 3 A
D2 HSU119
1 2
U8 74HC14 C66 0.1u
L
H SW2 PDN
4.096MHz X1
1 2
R49 1M
JP40 XTE
B
C67 5p
C68 5p
B
D3V JP41 MCLK2 JP42 512fs2
10 11 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 VD Q9 Q10 Q11 DGND Q12 RST CLK 9 7 6 5 3 2 4 13 12 14 15 1
EXT_MCLK2
J13 EXT1
XTL EXT1 R50 51 JP44 EXT1
256fs2 128fs2 64fs2 32fs2 16fs2 BCFS2 1fs2
BICKA BICKB JP43 BICK2_SEL
EXT_BICKA EXT_BICKB
16
C69 0.1u
8
U9
74HC4040 LRCKA LRCKB EXT_LRCKA EXT_LRCKB
A
A
JP45 LRCK2_SEL
Title Size Document Number
AKD4671-B
CLOCK
Sheet Rev
A2
Date:
A B C D
0 3
of
Wednesday, April 04, 2007
E
5
A
B
C
D
E
D3V
E
PORT1
VCC GND OUT 3 2 1
L10 (short)
1 2
E
C70 0.1u
C71 0.1u
TORX141
R51 470
C72 10u + + C73 0.1u R52 18k
39 38 37 INT1
VCC
48 46 44 47 43 42 45 41
C74 0.47u
40
U10
12 11 10 9 8 7
D
TEST1
RX3
RX2
RX1
RX0
AVSS
R
VCOM
AVDD
NC
NC
H L
123456
D
------OFF------
S1 SW DIP-6
1
IPS0
INT0
36
4114_INT0
DIF2 DIF1 DIF0 OCKS1 CAD0 I2C
1 2 3 4 5 6
2
NC
OCKS0
35
3
DIF0
OCKS1
34
CAD0 I2C
7 6 5 4 3 2 1
4
TEST2
CM1
33
5
DIF1
CM0
32
C
6
NC
RP1 47k
7 DIF2
AK4114
PDN
31
4114_PDN C75 5p MCKO JP46 4114_MCKI X2 11.2896MHz
C
XTI
IPS1
XTO
9
P/SN
DAUX
28
2
8
29
1
30
C76 5p DAUX
10
XTL0
MCKO2
27
11
XTL1
BICK
26
4114_BICK
B
B
12
VIN MCKO1 COUT UOUT DVDD BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1
SDTO
25
4114_SDTO
C77 0.1u +
C78 0.1u +
13
14
15
16
17
18
19
20
21
22
23
24
4114_LRCK C79 10u C80 10u
PORT2
IN VCC
A
4114_MCKO
3 2
C81 0.1u
1
A
GND
TOTX141
Title Size Document Number
AKD4671-B
DIR/DIT
Sheet
E
Rev
A3
Date:
A B C D
0 4
of
Wednesday, April 04, 2007
5
A
B
C
D
E
EXT_BICKA VCC D3V
3 4 5 6 7
THR INV JP47 BICKA PHASE
VCC2
U11
3 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 21 20 19 6 18 7 17 16 15 14 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8 9 10
U12
A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 21 20 19 18 17 16 15 14 7 6 5 4 3 2 1
JP62 BICKA 4670_BICKA 4670_SYNCA JP63 SYNCA
E
EXT_LRCK EXT_BICK
E
4670_LRCK 4670_BICK
EXT_LRCKA
4 5
R53 10k
MCLK BICK LRCK SDTI VCC
1 3 5 7 9
2 GND 4 GND 6 8 10 SDTO
7 6 5 4 3 2 1
8 9 10
EXT_MCLK2
MCLK2 BICKA LRCKA SDTIA VCC R54 10k
1 3 5 7 9
2 GND 4 GND 6 8 10 SDTOA
RP2 47k
2 1 DIR VCCA GND GND GND 13 OE VCCB VCCB 22 24 23
RP3 47k D3V
Baseband
RP4 47k
2 1 DIR VCCA GND GND GND 13 OE VCCB VCCB 22 24 23
RP5 47k
Slave
DSP
C83 0.1u
11 12
BICKA
C82 0.1u
11 12
C84 0.1u SDTOA1 JP50 SDTOA LOOP SDTIA VCC U13
C85 0.1u
Master
BICKB
JP48 M/S
JP49 PLLBT
74AVC8T245
74AVC8T245
D
D
3
A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
21 20 19 18 17 16 15 14
4670_SDTO
DAUX I2C MCLK2 JP51 ADC SDTI_SEL 4114_SDTO DIR
3 4
4 5
D3V
I2C
6
4670_I2C JP57 I2C PIN
7 8
U14
A1 A2 A3 A4 A5 A6 A7 A8
VCC
21 20
MCKO
9 10
4670_MCKO
B1 B2 B3 B4 B5 B6 B7 B8
4670_SDTI
2 DIR VCCA GND GND GND 13 OE VCCB VCCB 22 24 23
1 2 3 4 5 6
1A 1Y 2A 2Y 3A 3Y Vcc GND
4Y 4A 5Y 5A 6Y 6A
8 9 10 11 12 13
EXT_MCLK
5 6
19 18 17 16 15 14
4670_MCKI
D3V
1
D3V C88 0.1u C87 0.1u
14 7
C86 0.1u
11 12
EXT_MCLK2
7 8 9
U15 74HC14
CSN/CAD0 CCLK/SCL
CAD0
C
I2C (CAD0) 4-WIRE JP52 CTRL_SEL
10
74AVC8T245
4-WIRE (CDTO) 4670_CDTO I2C (ACK)
C
2 1
DIR VCCA GND GND
OE VCCB VCCB GND
22 24 23
JP53 CTRL_SEL2
R55 10k
R56 10k
R57 10k
C89 0.1u
11 12
C90 0.1u
13
10 8 6 4 2
9 7 5 3 1
CSN CCLK/SCI CDTI/SDA CDTO/SDA(ACK)
R58 R59 R60
470 470 470
74AVC8T245
VCC2 U16
1 3 5 9 11 13 14 1A 2A 3A 4A 5A 6A Vcc 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12
CTRL
R61 1k CDTI/SDA
EXT_BICKB
INV JP54 THR BICKB PHASE
3
U17
A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 21 20 19 18
JP64 BICKB 4670_BICKB 4670_SYNCB JP65 SYNCB
B
EXT_LRCKB VCC2
4 5 6 7 7 6 5 4 3 2 1
C91 0.1u
7
B
GND
74LVC07
U18 JP61 SDTIB
17 16 15 14 7 6 5 4 3 2 1
8 9 10
DOUT 10
8 6 4 VCCIO 2
9 7 5 3 1
SDTIB DIN CSN SCLK
4
1A1
1B1
13
EXT_MCLK2 4670_SDTIB
MCLK2 BICKB LRCKB SDTIB VCC R62 10k
1 3 5 7 9
2 GND 4 GND 6 8 10 SDTOB
SDTIA
5
1A2
1B2
12
4670_SDTIA JP60 SDTIA
Bluetooth
RP6 47k
2 1 DIR VCCA GND GND GND 13 OE VCCB VCCB 22 24 23
RP7 47k
CTRL SAR ADC
2
1DIR
1OE
15
D3V
C92 0.1u
11 12
JP56 D3V D3V
SDTOB1
6
2A1
2B1
11
4670_SDTOB
C93 0.1u
SDTOA1
7
2A2
2B2
10
4670_SDTOA SDTOB1 JP55 SDTOB LOOP SDTIB C94 0.1u
74AVC8T245
3
2DIR
2OE
14
D3V
A
1
C95 0.1u
8
VCCA
VCCB
16
A
GND
GND
9
74AVC4T245
Title Size Document Number
AKD4671-B
LOGIC
Sheet Rev
A2
Date:
A B C D E
0 5
of
Wednesday, April 04, 2007
5

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